1. Field of the Invention
This invention relates generally to integrated circuits and in particular to floating gate transistors.
2. Description of the Related Art
Programmable memories and logic circuits are integral parts of a digital system, such as a computer, and can have similar physical structures. One type of programmable memories is an electrically erasable and programmable read only memory (EEPROM), which is a reprogrammable nonvolatile memory that is widely used in the computer system for storing data both when power is supplied or removed. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (i.e., floating) gate that controls electrical conduction between source and drain regions. Data is represented by charges stored on the floating gate and the resulting conductivity obtained between the source region and the drain region.
Recently, logic circuits based on programmable memories have been introduced. The logic circuits are implemented by field programmable logic arrays (FPLAs) which provide a flexible architecture via user-programmed on-chip fuses (i.e., switches) to perform specific functions for a given application. The FPLAs are fabricated with floating gate transistors similar to the programmable memories. However, the floating gate transistors in the FPLAs act as switches rather than as storage elements. A common problem among the programmable memories and the related FPLAs is a large cell size, which limits circuit density.
The present invention provides floating gate transistors with vertical bodies and horizontal gates stacked next to the corresponding vertical bodies. In one embodiment, the floating gate transistor includes a pillar of semiconductor material extending outwardly from a working surface of a substrate to form a source region, a body region and a drain region of the floating gate transistor. A floating gate is formed along one side of the pillar, and a control gate overlays the floating gate. In one embodiment, the pillar is formed by etching as part of the first steps in fabricating the floating gate transistor.
Electronic charges are selectively stored in the floating gate in programming the floating gate transistor. An absence or presence of stored charges on the floating gate determines a conductivity state of the transistor between the source region and the drain region. In one embodiment, hot electron injection is used to program the floating gate transistor. In an alternate embodiment, Fowler-Nordheim tunneling is used to program the floating gate transistor.
In one embodiment, floating gate transistors form an array. The array includes a plurality of semiconductor pillars arranged in rows and in columns. The pillars form respective bodies of the floating gate transistors. A plurality of floating gates forms in trenches between the columns of pillars, and the floating gates are separated from respective sides of the pillars by a gate dielectric. A plurality of control gates overlay the respective floating gates, and the control gates are separated from the respective floating gates by an intergate dielectric.
In one embodiment, the pillars are etched as part of an initial fabrication step to extend vertically from a substrate. For example, each body of the respective floating gate transistors extend outwardly from the substrate with a source region formed proximally to the substrate, a body region above the source region, and a drain region above the body region.
In one embodiment, two floating gates lie adjacent to each other in each trench between the columns of semiconductor pillars, and one control gate overlays the adjacent floating gates. In an alternate embodiment, one floating gate lie in each trench between the columns of semiconductor pillars, and one control gate overlays the floating gate. In another embodiment, two floating gates lie adjacent to each other in each trench between the columns of the semiconductor pillars, and two corresponding control gates lie adjacent to each other above the floating gates.
In one embodiment, an array of floating gate transistors is a memory cell array with the source regions of common rows electrically connected to be first input selection lines, the control gates electrically connected along the direction of the columns to be second input selection lines, and the drain regions of common columns electrically connected to be output data lines. In an alternate embodiment, an array of floating gate transistors is a logic array with the source regions of a common column electrically coupled to be selection lines during programming of the logic array, the control gates electrically coupled along the direction of the columns to be inputs to the logic array, and the drain regions of a common row electrically coupled to be output lines of the logic array. In another embodiment, an array of floating gate transistors is a field programmable logic array with the source regions of a common column electrically interconnected, the drain regions of a common row electrically interconnected, and the control gates interconnected along the direction of the columns.
Charges stored in the floating gates of a memory cell array represent data of the memory cell array. In one embodiment, hot electron injection is used to selectively place charges in the respective floating gates of the memory cell array, thereby writing data memory.
In one embodiment, a floating gate transistor is fabricated upon a substrate. The floating gate transistor includes a first conductivity type semiconductor pillar formed upon the substrate. The pillar has top and side surfaces. A first source/drain region of a second conductivity type forms in a portion of the pillar that is proximal to an interface between the pillar and the substrate. A second source/drain region of a second conductivity type forms in a portion of the pillar that is distal to the substrate and is separated from the first source/drain region. A gate dielectric forms on at least a portion of one side surface of the pillar. A floating gate forms substantially adjacent to a portion of the side surface of the pillar and is separated therefrom by the gate dielectric. An intergate dielectric forms on a top surface of the floating gate. A control gate substantially overlays the floating gate and is insulated therefrom by the intergate dielectric.
Electrical charges in the floating gate controls electrical conduction between the first source/drain region and the second source/drain region of the floating gate transistor. In one embodiment, the floating gate transistor is a data storage element in a programmable memory array with the data represented by charges stored in the respective floating gates.
In one embodiment, fabrication of the floating gate transistors includes using a sacrificial gate layer to define a gate length. The sacrificial gate layer is selectively removed and replaced with a floating gate in a subsequent step. In one embodiment, the sacrificial gate layer is undoped oxide, and the floating gate is doped polysilicon.
In one embodiment, dopant layers are on top and bottom respectively of a sacrificial gate layer. The dopant layers and the sacrificial gate layer form in a trench defined by pillars of semiconductor material which form source, body and drain regions of transistors. In one embodiment, the sacrificial gate layer substantially aligns with the body region in the horizontal direction. The bottom dopant layer substantially aligns with an interface between the source and body regions, overlapping both regions in the horizontal direction. The top dopant layer substantially aligns with an interface between the drain and body regions, overlapping both regions in the horizontal direction.
In one embodiment of a fabrication process, heat treatment is used to form self-aligned transistor structures. For example, diffusion of the dopant layers during the heat treatment results in lightly doped source/drain regions in the body region. The lightly doped source/drain regions act as extensions of the source and drain regions respectively. The separation distance between the lightly doped source/drain regions is partially controlled by the thickness of the sacrificial gate layer. When the floating gate replaces the sacrificial gate layer, minimal gate overlaps occur with the lightly doped source/drain regions.